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Leads end-to-end power, performance, and area optimization for AI semiconductor SoCs. Influences architecture, RTL, memory hierarchies, dataflows, floorplanning, multi-voltage domains, synthesis, placement, clock-tree synthesis, routing, and power-analysis workflows. Partners with architecture, RTL, physical design, EDA vendors, and software teams to develop custom methodologies and deliver energy-efficient silicon under stringent PPA constraints.

Develop and optimize AI models for efficient inference on custom silicon. Build fine-tuning pipelines, implement acceleration techniques (quantization, sparsity, distillation), create benchmarking and profiling tools, and collaborate with hardware, compiler, and quantization teams to translate algorithmic improvements into real hardware gains.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Design and implement graph compiler optimizations (fusion, quantization, tiling) to convert TensorFlow/PyTorch models into IR, improve performance and hardware utilization, collaborate with ML researchers and hardware architects, and lead a team focused on compiler and code-generation improvements.