Design and implement graph compiler optimizations (fusion, quantization, tiling) to convert TensorFlow/PyTorch models into IR, improve performance and hardware utilization, collaborate with ML researchers and hardware architects, and lead a team focused on compiler and code-generation improvements.

The Senior Emulation Engineer will validate AI accelerator architectures, maintain emulation platforms, develop testbenches, and collaborate on performance optimization and debugging processes.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.