Teams at N Human Resources & Management Systems

Perform VLSI physical design from RTL handoff through tapeout, including floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, physical verification, ECO implementation, and DRC/LVS signoff. Collaborate with STA, DFT, and RTL teams on block-level closure and support full-chip integration activities.

Own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout. Develop SDC and UPF constraints, perform equivalence checks, close timing across corners and modes, generate manual ECOs, and resolve timing and DRC violations. Lead a team of 4–5 engineers and collaborate with RTL and Physical Design teams on block, subsystem, and full-chip SoC timing closure.

Own DFT architecture and implementation from RTL through tapeout, including scan insertion, ATPG, MBIST/LBIST, boundary scan, compression, test-point insertion, fault coverage, and silicon debug. Collaborate with RTL, physical design, and STA teams to achieve testability closure, while leading and mentoring 3–4 DFT engineers.