About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
This position is with ASIC design physical implementation (PD) team part of Custom compute and Storage business unit at Marvell. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM’s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools.
What You Can Expect
- Execute and deliver block/chip level place and route from RTL to GDS for different Marvell BU products.
- Interact with FE/BE design teams to prepare good floorplan and suggest appropriate changes to achieve PPA goal.
- Interact with design team to understand timing, CTS goals in detail to solve problems and propose physical design ideas.
- Debug timing constraint issues and feedback to design team.
- Debug LP issues and feedback to design team.
- Setup and run physical design steps Floorplan, PG Mesh Creation, Placement, CTS, Routing optimizations to achieve PPA goal.
- Check Logic equivalence from pre layout to post layout netlist.
- Analyze timing within PD environment and using STA tools and achieve timing closure by generating and applying ECOs to layout.
- Interact with PV team to analyze DRC/LVS/ANT/ERC results and achieve PV closure.
- Analyze results from PGV, fix IR drop issues and achieve closure.
- Develop perl/tcl scripts for generic tasks as required.
What We're Looking For
- BE/BTech/ME/MTech/ in E&C, EEE or related fields and 5-12 years of related professional experience in block/chip level Physical Design execution
- Solid understanding and hands on experience in physical design tasks Floor-planning, PG mesh creation, placement, CTS and Routing for complex blocks
- Excellent knowledge on timing constraints, static timing analysis, debug problems and closure.
- Hands-on understanding of DRC/LVS/ANT/ERC issues and closure
- Good knowledge on IR drop, ESD, EM issues and fixes
- Good knowledge on low power concepts and application to PD
- Experience with cutting edge technology node designs like 16nm, 12nm, 7nm
- Ability to plan and work independently and coordinate with cross functional teams
- Scripting skills using perl/tcl
- Good communication skills and ability work as a team
- Hands on expertise with industry standard EDA tools including but not limited to Design Compiler/RTL Compiler, Innovus/ICC2, Primetime/Tempus, QRC/StarXT, Calibre
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
#LI-KP1
