The Opportunity
We're looking for the Wavemakers of tomorrow.
Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.
What you'll do:
- Be a senior member of Alphawave central DFT methodology group responsible for developing flows across all company departments and projects
- Architect methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across company IPs, chiplets and SoC designs.
- Develop automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification.
- Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Creating automated QoR checks for implementation quality control.
- Write static timing constraints, create waivers, and devise flows for bullet proof timing checks
What you'll need:
- Engineer with proven technical and people management skills
- Collaborative team player, and out of the box mindset
- Good understanding in Verilog/VHDL and System Verilog
- Exposure with CAD and automation. Good exposure for using Perl techniques in creating generic codes. Knowledge of TCL and Python.
- Experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
- Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs.
- Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.
- Experience in scripting/reviewing SCAN/MBIST timing constraints.
- Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions.
Good to have:
- Bachelor's degree in engineering science, Electrical and Computer Engineering or Computer Science
- 4-6 years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles.
- Experience to various DFT EDA tools from Tessent, SNPS and Cadence
- Experience in core wrapping, pattern retargeting & packetizing ATPG techniques. SSN knowledge.
'' We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
- Competitive Compensation Package
- Restricted Stock Units (RSUs)
- Provisions to pursue advanced education from Premium Institute, eLearning content providers
- Medical Insurance and a cohort of Wellness Benefits
- Educational Assistance
- Advance Loan Assistance
- Office lunch & Snacks Facility
Equal Employment Opportunity Statement
Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.
