The Lead Design Engineer will focus on ASIC Design and Verification, specifically in the PCIe and Storage domains. Responsibilities include debugging and effective communication of technical issues while leading design initiatives.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.
We’re doing work that matters. Help us solve what others can’t.
Top Skills
Asic
Litera Thāne, Mahārāshtra, IND Office
Centrum IT Park, Wagle Estate, #610, , Thāne, Maharashtra , India, 400604
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