This internship focuses on yield improvement in semiconductor manufacturing by analyzing process flows and wafer edge performance to reduce yield losses through data-driven methodologies.
Our vision is to transform how the world uses information to enrich life for all.
Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
Location:
F10 Singapore. 1 North Coast Drive
Department:
Process & Equipment Engineering
Project Title:
F10 N and W Complementary Metal Oxide Semiconductor Matching and Wafer Edge Exclusion Optimisation
Project Description:
This internship project focuses on yield improvement through advanced process analysis and wafer edge performance optimisation within semiconductor manufacturing. The intern will examine matching behaviour between N and W process flows and evaluate wafer edge exclusion performance to reduce yield losses attributed to edge-related effects. The project emphasises data-driven analysis, defectivity characterisation, and inspection metric enhancement to enable sustained manufacturing performance.
Objective of the Project:
The objective is to identify key contributors to process mismatch and wafer edge yield loss, and to develop analytical methodologies that strengthen yield performance and inspection accuracy in a production environment.
Project Scope:
The project involves analysing inline, defect, and inspection data across modules to uncover root causes of yield variation. Scope includes evaluation of bevel and wafer edge behaviour, assessment of process sensitivity, and development of improved inspection algorithms to better represent true edge exclusion performance.
Learning Opportunities:
The intern will gain hands-on exposure to semiconductor process integration, yield analysis methodologies, statistical data analysis, and defect inspection systems. The role develops problem-solving skills, engineering judgement, and experience working with multi-functional engineering team members.
Deliverable:
Key deliverables include closure of an estimated N and W yield gap of approximately 0.9%, advancement of wafer edge exclusion targets towards zero non-live dies at a defined edge exclusion width, and the development of an improved wafer inspection algorithm that excludes known non-process detractors while accurately reflecting edge performance.
Impact of Project:
The project contributes directly to improved yield stability, enhanced inspection accuracy, and stronger manufacturing decision-making based on robust data insights.
Skillsets Required:
Analytical thinking, semiconductor process knowledge, statistical data analysis capability, defectivity interpretation skills, and the ability to translate data findings into engineering insights.
Course of Interest:
Microelectronics, Electrical Engineering, Chemical Engineering, Materials Science, Semiconductor Physics, or related engineering disciplines.
Duration Period:
Minimum a semester-long, full-time internship of at least 5 months.
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.
To learn more, please visit micron.com/careers
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
To request assistance with the application process and/or for reasonable accommodations, please contact [email protected]
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.
Location:
F10 Singapore. 1 North Coast Drive
Department:
Process & Equipment Engineering
Project Title:
F10 N and W Complementary Metal Oxide Semiconductor Matching and Wafer Edge Exclusion Optimisation
Project Description:
This internship project focuses on yield improvement through advanced process analysis and wafer edge performance optimisation within semiconductor manufacturing. The intern will examine matching behaviour between N and W process flows and evaluate wafer edge exclusion performance to reduce yield losses attributed to edge-related effects. The project emphasises data-driven analysis, defectivity characterisation, and inspection metric enhancement to enable sustained manufacturing performance.
Objective of the Project:
The objective is to identify key contributors to process mismatch and wafer edge yield loss, and to develop analytical methodologies that strengthen yield performance and inspection accuracy in a production environment.
Project Scope:
The project involves analysing inline, defect, and inspection data across modules to uncover root causes of yield variation. Scope includes evaluation of bevel and wafer edge behaviour, assessment of process sensitivity, and development of improved inspection algorithms to better represent true edge exclusion performance.
Learning Opportunities:
The intern will gain hands-on exposure to semiconductor process integration, yield analysis methodologies, statistical data analysis, and defect inspection systems. The role develops problem-solving skills, engineering judgement, and experience working with multi-functional engineering team members.
Deliverable:
Key deliverables include closure of an estimated N and W yield gap of approximately 0.9%, advancement of wafer edge exclusion targets towards zero non-live dies at a defined edge exclusion width, and the development of an improved wafer inspection algorithm that excludes known non-process detractors while accurately reflecting edge performance.
Impact of Project:
The project contributes directly to improved yield stability, enhanced inspection accuracy, and stronger manufacturing decision-making based on robust data insights.
Skillsets Required:
Analytical thinking, semiconductor process knowledge, statistical data analysis capability, defectivity interpretation skills, and the ability to translate data findings into engineering insights.
Course of Interest:
Microelectronics, Electrical Engineering, Chemical Engineering, Materials Science, Semiconductor Physics, or related engineering disciplines.
Duration Period:
Minimum a semester-long, full-time internship of at least 5 months.
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities - from the data center to the intelligent edge and across the client and mobile user experience.
To learn more, please visit micron.com/careers
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.
To request assistance with the application process and/or for reasonable accommodations, please contact [email protected]
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
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